1. Field of the Invention
The present invention relates generally to controlling the flow of program instructions in a microprocessor system, and more particularly, to controlling the flow of program instructions in a microprocessor system through the use of xe2x80x9cfencesxe2x80x9d or xe2x80x9cfencingxe2x80x9d control operations.
2. Background Information
Typical computer systems use a single central processing unit (CPU), known as a microprocessor. This microprocessor executes the programs stored in main memory by fetching their instructions, examining them, and then executing them one after another according to their programmatic order.
More advanced microprocessors utilize out-of-order processing or speculative processing, rather than in-order processing, to improve microprocessor efficiency by exploiting parallelism in the programs or pipelining capabilities of the microprocessor. In out-of-order processing, a software program is not necessarily executed in the same sequence as its source code was written. In speculative processing, branch prediction is performed pending resolution of a branch condition. Once the individual microinstructions are xe2x80x9cdispatchedxe2x80x9d and subsequently executed, their results are stored in a temporary state. Finally, microinstructions are xe2x80x9cretiredxe2x80x9d once all branch conditions are satisfied or once out-of-order results are determined to be correct. Examples of these microinstructions include xe2x80x9cwritexe2x80x9d (sometimes referred to as a xe2x80x9cstorexe2x80x9d) instructions to write data into memory, and xe2x80x9creadxe2x80x9d (sometimes referred to as a xe2x80x9cloadxe2x80x9d) instructions to read data from memory. The success of out-of-order or speculative processing depends in part on the accuracy, consistency, and synchronization of the data that they process.
Invariably, there will be locations in a program where one or more sets of instructions or their associated operations will need to rely on the results of a previous (e.g., programmatically earlier) instruction or operation. Fencing control operations (or simply xe2x80x9cfencesxe2x80x9d) have been used to synchronize the operation of the microprocessor in these situations. For example, in an out-of-order execution microprocessor, a special form of a xe2x80x9cstore addressxe2x80x9d microoperation fences all memory access and retires all execution results up to the store address microoperation. This fencing control operation prevents all loads from dispatching until the fence itself has been dispatched and has completed execution. The use of such a fence is needed to insure that the wrong data is not loaded or stored.
There are several situations when fences or fencing control operations are required, in addition to the situation where a program is being processed in an out-of-order or speculative manner. These include mode changes (e.g., a change from a real mode of operation to a protected mode of operation), lock operations (sometimes referred to as xe2x80x9csemaphoresxe2x80x9d), serializing instructions, changes of memory type, and input/output (I/O) operations, etc. Prior art microprocessors typically address all of these situations by performing only one type of fencing control operation, regardless of the instructions or conditions that give rise to the fencing requirement. The typical single fencing control operation is to drain all xe2x80x9csenior stores,xe2x80x9d which are data that are past retirement and being stored in buffers but are not yet committed to architectural or system state (e.g., to a cache or memory).
However, the process of draining all senior stores whenever a fencing need arises can exact a heavy toll on the efficiency of the microprocessor. It may take a long time for the senior stores to drain. Perhaps these may never drain if data is continuously being fed into the bus. Also, some instructions, operations, memory transactions, or conditions that give rise to the need for fencing do not necessarily require the draining of all, or perhaps any, of the senior stores. Hence, the existing xe2x80x9cone size fits allxe2x80x9d single fencing approach unnecessarily delays the execution of some types of instructions. This situation is further complicated in computer systems that may use multiple microprocessors, where the single fencing approach would unnecessarily delay execution of programs in more than one microprocessor.
Accordingly, a more versatile and flexible approach to meeting fencing requirements is desired.
According to an aspect of the invention, a method is provided in which a processor detects a selected one of an instruction or a condition. In response, the processor dependently performs a selected one of a plurality of predetermined control operations to effectuate a desired synchronized state for the processor. The processor dependently performs the selected control operation based at least in part on the nature of the instruction or condition.